The memory capacity of large-scale semiconductor memory devices such as DRAMs is increasing, and mass production of DRAMs having an internal memory capacity of 4 gigabits is already under way. In addition, DDRSDRAMs (Double Data Rate Synchronous DRAMs) exchange read/write data with an external device in synchronization with both rising and falling edges of a clock, thereby achieving high-speed data transfer as a system. Products capable of inputting/outputting such read/write data at a transfer rate exceeding 1 Gbps are beginning to appear.
In addition, there are cases where the memory bit number exceeds 32, depending on the intended use. Thus, there is needed a product capable of inputting/outputting data in parallel through the same number of data input/output terminals (DQ terminals). Such product needs to be able to simultaneously input/output multi-bit read/write data in parallel through the data input/output terminals (DQ terminals) and execute high-speed data transfer with large-capacity memory cell arrays.
Patent Document 1 discloses a semiconductor device including a semiconductor chip, and pads are arranged in a line in a peripheral section of the semiconductor chip.